Skew Minimization Problem with Possible Sink Displacement

In applications such as design of integrated circuits (chips), it is sometimes required to connect the terminals (receivers) and the central vertex (source) by a weight-minimal tree where the signal delays between the source and the terminals are the same or differ by a minimal value. Simple necessary conditions for existence of the desired tree, heuristic rules for displacement of the terminals for which these conditions are not satisfied, and a new polynomial algorithm to determine an approximate solution were presented. 1. FORMULATION OF THE PROBLEM As the need for high-speed integrated circuits (chips) is growing from one year to the next, design of their signal systems becomes pivotal. The signal network is responsible for clocking the computer system. The command signal is generated outside the chip and fed into it through the input (source or root). Each functional element for which the signal is destined is connected to the source via a signal network. Each element performs a series of logic operations (functions) and until the beginning of the next cycle of computations waits for a signal to transmit the results to other element(s). Thereby the flows of information within the computer system are checked. The clock skew is the maximum difference between the instants of signal arrivals to different system components. Its increase results in lower speed of computations. In the existing systems where the size of elements is substantially smaller than one micron, clock skew is one of the main factors defining operation of the system. It reduces the clock frequency because the time between two successive signals must be increased so as to enable all system components to receive the signal. It is currently believed that the clock skew in the high-speed circuits should not exceed 5% of the maximum (critical) signal transmission time (critical delay). As will be shown in what follows, it does not always happen that there are clock trees with zero clock skew. In such an event, it is sometimes admitted to displace the terminals from their initial positions at a distance of at most two units. The possibility of displacing the terminals makes the construction of the zero-skew clock tree especially difficult. The problem of constructing a min-skew clock tree is known to be NP-hard [3] even without displacement of the terminals. The problem of clocking the arrivals of command signals to the elements of integrated circuit can be stated as follows. Each terminal (circuit element) executes certain operations. All terminals execute part of the general program, and their operation must be coordinated. The requirement of simultaneous arrival of signals to all terminals can be satisfied if one constructs a tree where all paths from the source to the terminals have identical delays. Additionally, from all the admissible trees the minimum-weight (cost) one must be selected in order to minimize the space occupied. In 1 This work was supported in part by the grants of KISTEP’99 and the Russian Foundation for Basic Research, project no. 02-01-00977. 0005-1179/03/6403-0493$25.00 c © 2003 MAIK “Nauka/Interperiodica”